1. Field of Invention
The present invention relates to integrated circuits and more particularly to modeling current and voltage relationships in integrated circuits.
2. Description of Related Art
Parasitic extraction has been an important part of integrated circuit (IC) design verification for at least a decade, and the sophistication of the extraction process has increased over this time. In general, these parasitic effects are undesired component interactions that result from increasingly compact and complex circuit designs, and their modeling (or extraction) has become increasingly important for verifying designs.
The assumption that devices themselves did not interact with one another and could be modeled by their compact models remained valid until relatively recently. However, the interaction between devices via the substrate has turned out to be critical to the performance of especially mixed-signal, analog and RF (radio frequency) circuits. Early parasitic extraction programs aimed to capture layout-dependent device parameters such as diffusion area and perimeter. As frequencies increased, interconnect parasitic capacitance, then resistance, then inductance were added to the models. Additionally, coupling capacitances and later mutual inductances between wires were added to the list of parasitic effects being captured to identify signal integrity problems in digital designs.
Recently, substrate extractors have been used to extract a resistor-capacitor network for the substrate. However, RF integrated circuits have been particularly problematic for extraction methodologies due to the use of embedded passive elements. Spiral inductors and metal-insulator-metal (MIM) capacitors are key to implementing RF functionality. However, these elements tend to interact among each other as well as with surrounding interconnect elements. In order to resolve these effects, IC modelers have developed quasi-static electromagnetic solvers that treat passive elements, such as inductors and MIM capacitors, as metal and models the entire metal structure together with the lossy substrate.
More recently, electromagnetic solvers (e.g., Virtuoso RF Designer Solver) have offered the same capability in fullwave (e.g., complete solutions to Maxwell's equations). See, for example, U.S. Patent Application Publication No. 2005/0076317 A1, “Method and apparatus for determining interactive electromagnetic effects among conductors of a multi-layer circuit” (Apr. 7, 2005), and “Large-scale Broad-band Parasitic Extraction for Fast Layout Verification of 3-D RF and Mixed-Signals On-chip Structures”, F. Ling et al., IEEE Transactions on Microwave Theory and Techniques, Vol. 53, No. 1, January 2005.
However, these fullwave solutions are generally computationally intensive and take a significant amount of time because of the large size of the corresponding matrices. Furthermore, it is generally difficult for IC designers to assess the effect of a relatively small incremental change in a design without a substantially redoing the calculations for the fullwave solution. As a result, these solvers are often used more as verification tools rather than design tools.
Therefore there is an need for IC modeling tools for determining accurate (e.g., fullwave) solutions that can be flexibly used when designs are incrementally adapted from other designs or design elements.